The Sonics verification methodology involves understanding of the various components involved in a design flow. The high degree of configurability in the product line creates unique challenges for the Verification Engineer as the verification space to be covered is extremely large.  A combination of approaches is required that run from property based formal verification to constrained random testing to directed testing that exercises the core of the configuration space.

Responsibilities:  

• Create verification plans and test suites
• Build/Document effective verification environment using Assertion Based Verification, Formal Verification, Coverage  Driven Verification and Constrained Random Techniques.
• Analysis of functional coverage and performance

• Debug designs and publish verification status
• Interaction with other members of the architecture group, the RTL
  implementation team and the software infrastructure team in order to understand product, design/validation and SW infrastructure implementation issues.
• Other duties as assigned.

Skills required:

• Experience with high level verification languages, i.e., SystemVerilog, Vera, TestBuilder, Specman or SystemC.
• Worked with multiple standard protocols. OCP, AHB, AXI, PCI. Etc.
• Strong programming skills in OOP, C++, SV, Python, SystemC, Verilog.
• Expertise in measuring/analyzing functional/code coverage metrics.
• Good spoken and written communication skills.
• Experience with SoC designs desirable.

Education/Experience:

-BS/MS/PhD in Computer Science or Electrical Engineering

-5-8 years work experience in System-on-a-Chip semiconductor verification.

Please forward Salary History and Requirements

 Apply at Jobs@sonicsinc.com