32 w32 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w64 0 0 1 0 1 0 1 0 0 0 1 0 0 1 1 1 little 1 1 1 1 0 1 0 0 1 0 32 w32 0 0 1 0 1 0 1 0 0 0 1 0 0 1 1 1 little 1 1 1 1 0 1 0 0 1 0 32 w32 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w64 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w64 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w64 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w64 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w64 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w64 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w64 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w64 0 0 0 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 0 0 0 0 0 0 0 1 1 1 1 w64 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 0 0 0 0 0 0 0 1 1 1 1 w64 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 0 0 0 0 0 0 0 1 1 1 1 w64 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 0 1 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 little 0 0 0 0 1 1 5 0 1 0 1 0 0 4 4 0 0 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 1 32 w32 0 1 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 little 0 0 0 0 1 1 5 0 1 0 1 0 0 4 4 0 0 0 1 0 1 1 0 1 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 1 32 w32 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 32 w32 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 32 w32 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 32 w32 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 32 w32 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 32 w32 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 32 w32 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 32 w32 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 32 w32 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 32 w32 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 32 w32 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 32 w32 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 32 w32 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 32 w32 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 32 w32 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 32 w32 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 32 w32 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 0 32 0 0 0 1 1 1 w32 0 1 0 0 0 1 0 1 1 1 0 1 0 0 1 0 0 32 0 0 0 1 1 1 w32 0 1 0 0 0 1 0 1 1 1 0 1 0 0 1 0 0 32 0 0 0 1 1 1 w32 0 1 0 0 0 1 0 1 1 1 0 1 0 0 1 0 0 32 0 0 0 1 1 1 w32 0 1 0 0 0 1 0 1 1 1 0 1 0 0 1 0 0 32 0 0 0 1 1 1 w32 0 1 0 0 0 1 0 1 1 1 0 1 0 0 1 0 0 0 snap_clk snap_clk ARMI performance fair none none 1 0 2 snap_clk ARMD performance fair none none 1 0 1 snap_clk DSP performance fair none none 1 0 0 snap_clk DDR2 performance fair none none 0 1 1 snap_clk SRAM performance fair none none 0 1 0 snap_clk snap_clk SATA performance fair none none 0 0 0 snap_clk DMA0 DMA1 DMA2 DMA3 performance fair none none 0 0 {0 0 0 0} 3 snap_clk OSD VENC DAC0 DAC1 DAC2 DAC3 performance fair none none 0 0 {0 0 0 0 0 0} 2 snap_clk CCD VIF PVE HSTG RSIZE performance fair none none 0 0 {0 0 0 0 0} 1 div_clk EMAC WLAN USB0 USB1 area fair inputs none 1 1 4 div_clk TMR0 TMR1 WatchDog PWM0 PWM1 PWM2 area fair inputs none 1 1 3 div_clk EMIF SMedia NAND SD MMC area fair inputs none 1 1 2 div_clk RS232 I2C SPI0 SPI1 UART0 UART1 area fair inputs none 1 1 1 div_clk RegDMA0 RegDMA1 RegDMA2 RegDMA3 RegSATA RegDSP RegVDEC RegVENC RegEMAC RegUSB1 RegUSB0 RegPVE RegDAC0 RegDAC1 RegDAC2 RegDAC3 area fair inputs none 1 1 0