Sonics Inc.is looking for an experience and hands-on team player of creativity and initiative that can provide innovation on platform and on-chip interconnect performance optimization projects. 

Responsibilities:

• Engaged in performance analysis and performance validation, at the architecture level and at the RTL behavior level, of Sonics system-on-a-chip interconnects and smart memory IPs.
• Responsible for creating/modifying new/existing C++ simulation models (some models can have up to 50K lines of code) of Sonics IPs and adding performance instrumentations to not only these models but also their RTL counterparts in order to understand architecture limitations and explore new architecture alternatives.
• Interact with other members of the architecture group and the RTL implementation team to understand application architecture requirements, implementation limitations, and infrastructure supports.
• Other duties as assigned 

Education/Experience:

• Experience in computer hardware simulation and modeling, and software design.
• Experience in analyzing and understanding complex computer HW/SW systems.
• Experience in performance debugging and optimization of HW systems running complex workloads.
• Experience in designing performance tools.
• Good spoken and written communication skills.
• Experience: must have work or academic experience in related fields.  
• MSCS/CE/EE with appropriate background and experience; Ph.D. is preferred.

Apply at Jobs@sonicsinc.com