SonicsMX

The SonicsMX SMART Interconnect solution contains a high performance advanced fabric and a comprehensive set of data flow services for the development of multicore SoCs. By utilizing state-of-the-art physical structure design and advanced protocol management, SonicsMX delivers guaranteed high bandwidth together with leading edge, fine-grained power management. Quality of Service, access security, and error handling features comprise a robust turn-key solution that facilitates higher design predictability and decreases chip development time.

 

Supporting multi-threaded and non-blocking communications, SonicsMX offers both crossbar and shared bus structures in an innovative distributed implementation. Compliance with Open Core Protocol (OCP), AHB, and AXI interfaces ensures maximum reuse of all cores regardless of their native configuration.

SonicsMX decouples the functionality of each core from the interconnect communications required among the cores. Configuring SonicsMX allows SoC developers to tailor the communications for each core’s specific needs while balancing latency, physical layout, clock frequency, area, and power consumption.

The SonicsStudio™ development environment supports SonicsMX by automating configuration, data analysis, and performance verification. A SystemC model is available to allow architectural modeling concurrently with application software development.