Sonics3220 SMART Interconnect solution is a  non-blocking peripheral interconnect that guarantees end-to-end performance by managing data, control and test flows between all connected cores.

Providing low latency access to a large number of low bandwidth, physically dispersed target cores, Sonics3220 uses a very low die area interconnect structure that facilitates a rapid path to simulation.

This SMART Interconnect solution handles incoming traffic from up to four initiators and can distribute those communication requests and responses to up to 63 targets. By eliminating blocking, Sonics3220 allows multiple transfers to be in flight at the same time while producing a more predictable performance model for cores on a Sonics3220 system. Core service requests can occur whether there is an ongoing transfer or not. In addition, because the Sonics3220 is non-blocking, there is no need for a multi-layered bus architecture, thus reducing costs and power consumption.

Sonics3220 supports the industry standard Open Core Protocol (OCP) and AMBA Peripheral Bus (APB) interfaces.