| 5 to 10 years ASIC design experience at the logic and architecture level. Design of complex chips or microprocessors or systems. Physical layout experience of computer chips. Customer interaction and problem resolution. ASIC design flow, including product specification, architecture, logic design, synthesis, static timing, Engineering Change Order (ECO) flow, layout. Experience with ASIC standard tools (Synopsys, Avanti, Cadence, Mentor, etc). Must have experience in dealing with or in front of customers. |
| RTL coding in either VHDL or Verilog. Programming skills with C, SystemC, C++, Perl, TCL and UNIX shell. ASIC or SOC design skills. Understanding of digital logic. Excellent presentation and communication skills essential. Fluency in English and a second major European language is required (preferably French). |