The MemMax Memory Scheduler is an intelligent DRAM access scheduler designed for use with an OCP compliant memory controller and Sonics SMART Interconnect™ solutions.
 

Ideal for high-bandwidth applications, MemMax’s sophisticated thread-based pipelining and advanced arbitration schemes reduces interconnect over-design and redundancy. By decoupling the functionality of the SoC from the DRAM, MemMax also encourages adoption of the DRAM technology that offers the best cost and performance value.

SoC designers can use compiled RAM to consolidate all of the flip-flop based buffers normally distributed among the various initiator cores into a single buffer within MemMax. This reduces the total SoC die area and lowers overall power consumption. When used with a Sonics SMART Interconnect solution, MemMax further reduces SoC costs by eliminating a substantial amount of the excess wires required by traditional wire-based, multi-layered bus architectures.