System-Level Design: January 2012Reverse Engineering
System Level Design Blog - The Traffic Cop: January 2012New Electronic World Order
System-Level Design: December 2011Too Many Standards, But Still Not Enough
System Level Design Blog - The Traffic Cop: December 2011Looking Back To The Future
System-Level Design: November 2011Build It Faster
System-Level Design: November 2011Make Vs. Buy
System Level Design Blog - The Traffic Cop: November 2011A Secret Weapon
EDA360 Insider: November 2011Sonics Founder Drew Wingard on the state of the art for SoCs, IP, System and SoC Realization
EE Times: November 2011Sonics sues Arteris for infringing patents
System Level Design Blog - The Traffic Cop: October 2011eDRAM: No Brainer... But No Takers?
System-Level Design: September 2011One-on-One with Sonics CEO, Grant Pierce
System Level Design Blog - The Traffic Cop: September 2011The High-Speed Virtual Highway
Chip Design Magazine: September 2011The Next NoC
EE Times: September 2011Sonics rolls GHz-class network-on-chip
Chip Design Magazine: September 2011Sonics and Others Evolve On-Chip Interconnections
System Level Design: August 2011Will Wide I/O Reduce Cache?
System Level Design Blog - The Traffic Cop: August 2011Summertime…And The Living (Isn’t) Easy
System Level Design: August 2011Wide I/O’s Impact On Memory
System Level Design: July 2011Solving Memory Subsystem Bottlenecks In 3D Stacks
System Level Design Blog - The Traffic Cop: July 2011High Stakes Domination
System Level Design: July 2011SoC Design in 5 Years
System Level Design: July 2011Experts at the Table: 2.5D Stacked Die (Part 1 | Part 2 | Part 3)
System Level Design Blog - The Traffic Cop: June 2011Playing Hardball with Software
System Level Design: June 2011 Tech Talk, Sonics’ CTO Drew Wingard
System Level Design Blog - The Traffic Cop: May 2011Powering Forward or Moon Walking?
System Level Design: April 2011 What If in 3D
System Level Design Blog - The Traffic Cop: April 2011Dawn of the M2M Age
SOCcentral: April 2011Sonics Viewpoint: IP Gets Smarter
System Level Design: March 2011 Fishing For Ideas In A Bigger Pond
System Level Design: March 2011 The Quest For A Better IP Integration Methodology
System Level Design Blog - The Traffic Cop: March 2011 Speeding Tickets
Low-Power Engineering: March 2011 Experts at the Table: Billion Gate Design Challenges (Part 1 | Part 2 | Part 3)
Semiconductor Manufacturing & Design: February 2011 Experts at the Table: 3D Stacking (Part 1 | Part 2 | Part 3)
System Level Design: February 2011 The Growing Importance Of Subsystems
System Level Design: February 2011 Memory, Bandwidth And SoC Performance
System Level Design Blog - The Traffic Cop: February 2011 Bridging The Gap
System Level Design: January 2011 Tailoring IP, Tools and Flows
EE Times Product Spotlight: September 2010 Sonics launches stand-alone memory scheduler IP block
EE Times Memory DesignLine: September 2010 Conquering the Memory Bottleneck
GSA Forum: June 2010 IP Innovation: At the Core of Consumer Electronics Design
Low Power Engineering: May 2010 IP Integration Creates Challenges For Power
EE Times: January 2010 Need to move beyond the network-on-chip
News Coverage Archive
Jodi Guilbault Sonics, Inc. +1 415 987-4970 jodi@sonicsinc.com