Moving SoC design... Beyond the NoC
I really like Sonics new web site that was launched a few weeks ago. I am not just talking about the cool icons and the colors (which are great!), I am also referring to the short flash animation on the homepage that zips by saying: “Moving SoC designs…” (then says) “beyond the NoC”. I want to clarify what this pithy expression really means. We were not trying to be obtuse, but I hope it got you thinking about NoC (network-on-chip) technology and how exactly Sonics is “Moving beyond the NoC?” This at first may seem strange, especially if you are familiar with a ‘pure’ NoC, then you will know this is a new technology that is just now migrating into designs. So why do we want to move beyond something that is targeted for production by late 2010 – 2011? Sonics is certainly researching technology that does in fact look several years out (that’s a post for another day) but what I want to discuss here is how Sonics has already made NoC technology practical in today’s production SoCs. Maybe “practical NoC” would not sound as interesting on the website.
Sonics recently announced that its customers have shipped over half a billion chips using Sonics technology. This diverse customer base has provided us with unique insights into the requirements of SoCs in a variety of markets. These markets range from high performance video SoCs, like the ones I discussed in my last blog entry, to low-cost embedded wireless SoCs like the ones used in Wi-Fi and cellular basebands. We’ve found that today’s SoCs are not simply a set of homogeneous cores communicating with each other, but rather a combination of bandwidth, frequency, latency and various protocols, coupled with complex area and power considerations. Any one single network topology would struggle to effectively meet the performance, cost (i.e. gate count) and power consumption requirements to design a successful SoC for these competitive markets.
For example, on a single SoC you can have high performance cores that require zero latency access to memory that are best served by a low-latency switch, while other cores that can tolerate latency are better served by a low-gate count bus merger or by a peripheral network that can span longer physical distances on the chip. In addition, all of these network configurations need to be very power-efficient, especially for mobile designs. To solve these challenges, chip designers need a wide range of network configuration options giving them the flexibility to introduce fast, low-latency network switches in the critical paths while trading off bandwidth and performance on other parts of the chip to save gates and power. Typical NoC implementations can incur latency as fewer wires are prioritized with fast clocks and simple network switches. Sonics has been providing designers with a scalable wiring solution while maintaining protocol features in order to offset latency. The messaging protocol utilized by the switches avoids the serialization penalty present in standard NoCs with minimal overhead in area and allows for more complex switching operations— thereby reducing pipeline depth and the corresponding latency.
In short, ‘moving beyond the NoC’ means blending the best of several different on-chip network technologies, giving chip designers the freedom to solve real connectivity and data flow problems. Backed by a wealth of applications and production experience, Sonics is in a unique position to meet the complex SoC design requirements of today and tomorrow. I guess you can say that we learned all this through the ‘school of hard NoCs’. (I know….but I couldn’t resist). Please check Sonics’ website for more information on NoC technology and products.
Frank Ferro
Director of Business Development at Sonics, Inc.
Tags: fabric, hd, IP, latency, network, NoC, on-chip network, performance, protocol, SoC, sonics, system-on-chip