Sonics, Inc. Chief Technology Officer (CTO), Drew Wingard, discusses the issues surrounding designing complex SoCs at GHz speeds. This talk was recorded on March 27, 2012 during the DesignWest ESC trade show at the San Jose Convention Center.
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If you’re paying attention and/or using a smart phone every day (and perhaps it’s safer to assume the latter) the ‘cloud’ is no longer a buzzword. The cloud has become grounded in our daily reality. How’s that for a paradox and a visual?
But at a minimum, it has become more like a punch line in every consumer’s day—without even thinking about it. Projections show that 15 billion devices and 3 billion people will be connected to the Internet by 2015. We all use the cloud daily for a large number of tasks, both personal and professional. Today, accessing information on the Internet is like breathing for most of us. Although I would likely never be accused of being a social media power user, I do have multiple email accounts in the cloud, use online storage, shop in the cloud, and perform a number of business functions that now reside in the cloud. There’s no ambiguity in that—the cloud is here, happening, and the silver lining is making its presence known to us all, ready or not.
Now as a mobile professional, I don’t want to have an Internet connection every time I need to read email. What would I do on those 10-hour flights? Security is also an issue because I am not entirely comfortable keeping valuable information in the cloud (although in reality, of course, I have plenty of information there). And like anything big, bold and not entirely understood, we are naturally skeptical. Storing music is safe, but my family photos, or backing up my entire hard drive…Hmmm. There is no question that this is the most convenient place to store information and having back-up copies in the cloud provides additional security benefits such as protection from disk crashes and physical calamities.
But no one can dispute that the cloud is growing and taking on a new level of significance as it seamlessly transitions from servers to mobile devices. Data center traffic is estimated to grow by 33% through 2015, with each of us generating 4GB of traffic per day. The cloud also has to deal with all those connected devices that require private clouds, public clouds, and a hybrid of both. These connected devices also offer new challenges for IT managers trying to control and secure an enterprise environment. All of this has clear implications for the number of servers and storage needed in the cloud, and in turn, is a major driver and an opportunity for semiconductor growth.
The ‘server on a chip’ is seen as an important growth market by semiconductor and IP vendors, which traditionally have focused on consumer devices. These ‘cloud-enabled’ SoCs are driving the leading edge of performance with multiple CPUs running at well over 1 GHz, with a high-speed switch fabric and a large number of high-speed peripherals.
The cloud/device co-efficient. The cloud also has been driving the features and functions for our SoCs in the popular gadgets we carry around today. Think about how useful (or is it useless) your tablet is without an Internet connection to the cloud. Sure, you can watch movies and play games, but those specialized portable devices have existed for years and never had the ubiquitous success that tablets have seen across all age groups—personally and professionally. And then think about how ‘smart’ your smart phone would really be without cloud content. A recent Nielsen survey of the top consumer devices showed that all of these products had connections to the Internet, with most having the ability to run downloadable user applications. And finally, consider the “Internet of Things,” a world where everything is uber-connected!
So the cloud is a true force behind the success of today’s connected devices and is driving the vast majority of their feature sets, and in turn, the underlying SoC. Much of the SoC architecture complexity is heavily driven by the need for connectivity and having the ability to accommodate downloadable user content. The graphics and video subsystems, for example, are increasing in performance to display this content faster and clearer. The communications subsystems are increasing in complexity since they have to connect to everything, to the point of making your mobile device a mini access point to the cloud—and who knows, maybe even becoming a baby or micro-cloud itself someday.
The co-existence of chips + cloud. The SoCs in these connected devices are now comprised of many computational subsystems (15 to 20 and growing). The computational rate of these subsystems are now outpacing Moore’s law; hence the need for multiple graphics and CPU cores to run in parallel, because we are not getting enough speed and density increases with each new process node to keep pace with all the content and applications. Looking inside any one of these subsystems and you will find multiple processing cores, memory, networks to connect the cores, coherent memory within the subsystem and interfaces to the main chip. To connect all these subsystems requires a higher-level network that may also include a coherency network layer on top to keep the memory shared across subsystems coherent.
Given all this, the SoC architecture is now comprised of networks-of-networks (aka the Internet), which has to run any number of user applications that may not be understood or identified at the time the SoC is designed. So the SoC continues to transform, from having simple buses to on-chip networks, to now many layers of networks (networks-of-networks). And with the amorphous nature of the cloud, it brings even more possibility and progress…without boundaries.
The cloud continues to scale before our eyes, both big and small, so fortunately for all of us, we can’t help but think about its infinite reach and what lies ahead for cloud-connected devices. And when we ponder today’s billions and tomorrow’s tens of billions of cloud-connected mobile devices, business requirements will naturally course-correct and change will be in the air…(and certainly in the cloud!) From the SoC’s vantage point, it looks as if it’s becoming strongly anchored in the cloud and not getting out anytime soon.
–Frank Ferro is Director of Marketing at Sonics.
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Speed is the shiny object, the undisputed premium, and in many ways, the ultimate carrot with customers when designing advanced SoCs. There are a few moments when the conversation temporarily shifts to area, or some special feature, but we always come back to speed, or more specifically, frequency. This is without a doubt the first and most important requirement ‘gate’ to pass through. If your product can’t meet the speed target, real or perceived, than it is difficult to advance the discussion to the next stage. And as we all know, the customer is always right even if they aren’t. But no one disputes the need for speed or its place on the throne.
SoCs Now. If we look at heterogeneous SoC implementations to date, the memory speed often outpaces performance—so running the processor and the system bus faster may not always be helpful to overall system performance. If this is true, then why run faster? There are several reasons from a customers’ perspective. If we look at mobile applications processors for example, it is difficult to know exactly what will run on the device given the large number of applications for mobile computing—and many of these applications need to run simultaneously. Having that extra speed will provide some confidence that the SoC can handle those times when peak bandwidth is demanded.
However, even with an initial high-frequency design specification, a single-channel DRAM subsystem still puts practical limitations on the bandwidth. Having multiple heterogeneous cores competing for DRAM, even with the best QoS algorithms, results in processors that spend time waiting for memory. Given this fact, the designer needs to find an optimization point for the system (by doing system performance analysis) that maximizes bandwidth with the most efficient use of system resources (i.e. frequency and gates). This is certainly a challenge today that has not yet been completely solved. And it doesn’t look like the SoC designer will get a chance to catch their breath on this one anytime soon, given that the market pressure is rapidly driving requirements for even higher levels of performance (i.e. SoC complexity).
SoCs or Compute platform. Going forward, SoC architectures are taking on the attributes of large-scale computing platforms with multiple CPU processors that have cache-coherent memory. So now the problem for the embedded SoC is more challenging in some ways. In addition to the CPU compute clusters, the system has to deal with all the other heterogeneous processor cores and subsystems with some cores needing to be cache-coherent with the CPU memory while other subsystems have real-time processing requirements. The challenge is further complicated by the fact that with embedded SoCs the memory is less distributed than a traditional computing environment, so the DRAM continues to be a potential bottleneck if special care is not taken. These new requirements are clearly putting pressure on the overall system to run faster. But by how much – 2X, 3X?
Let’s look at an SoC with the CPU(s) running at 2GHz as an example (the target speed for next-generation tablet processors). In this SoC, the on-chip network performance after the cache will need to be 1GHz or half the processor speed. Compare this to applications processors that are in the market today with the on-chip network speeds typically running at about 200MHz to 400MHz with an 800MHz processor (one quarter or half the processor speed). We now need at least a 2.5X to 5X speed increase in the network to keep pace with the latest processors. But again we have to ask the question: Do I really need to run this fast or am I just wasting performance that I can’t utilize? To answer this question, we can look at two of the new architectural components of the SoC: cache coherency and multi-channel DRAM.
Adding hardware cache coherency to the embedded SoC is intended to speed performance by reducing the number of times you need to access external DRAM. This ultimately translates into a better user experience when running applications on the mobile device. Having cores outside the processor cluster, like the GPU, remain coherent with the CPU cache will require transactions like cache-to-cache data transfers. As mentioned above, the processor cache usually runs at half the speed of the processor, so the on-chip network speed will need to support transfers at 1GHz to be able to support these types of transactions.
The need for increased bandwidth is also forcing the memory subsystem to support multiple channels of DRAM. Having multiple channels expands the memory bandwidth allowing for a peak data rate increase. Looking specifically at the wide I/O memory (planned for use in mobile application processors), it has 4 channels of 16 byte DRAM running at 266.6MHz. Here it is easy to envision an application that will demand full memory bandwidth so provisioning the GPU interface, for example, to take full advantage of the entire memory bandwidth across all channels ensures peak performance when needed. Again, to support this level of performance requires a network speed of 1066MHz (266.6MHz x 4).
Is the customer always right? In this case by asking for more speed and headroom, they were clearly anticipating the SoC architectural evolution that is now taking place for the next-generation of SoCs. The previous two examples would say the answer is yes—more speed designed into the system ensures that the SoC will cover the widest set of use cases supporting a host of current and new applications. So when a customer tells you they require 2X the speed—listen. They are usually on to something.
–Frank Ferro is Director of Marketing at Sonics.
As the fabless era disaggregated EDA and IP offerings, there are areas where in- house development is still the norm, even with today’s $2.5B IP industry. One of these is on-chip network – connecting the IP cores and memory subsystem.
On-chip interconnect or networks-on-chip (NoCs), in many companies, is still regarded as a part of the IP that can be internally developed for SoCs. With deeper process nodes, such as 28nm, enabling device convergence, more cores are included in the SoC, accelerated further by subsystems.
Today, many of the industry analysts have highlighted mobile markets— including Ultrabooks, Smart Phones and Tablets as the new high-growth semiconductor SoC markets. These designs can include well over 100 IP cores combined with multiple subsystems connected across multiple supply voltages (to enable DVFS) and dozens of switched power domains, in addition to 6-12 clock domains and a multitude of switched clock domains. The SoC is getting smarter and its processing systems faster, putting increasing pressure on the power management system to control where power is used to maximize the user experience while extending battery life and meeting thermal constraints. This perfect storm of overlapping constraints puts massive pressure on the on-chip-network that provides the connectivity between the cores, funneling data to the memory system and enabling the seamless connectivity/control of all the IP cores spread across the power and clock domains. This is an essential, differentiating function as designers try to navigate all the system-level requirements for today’s application processors.
Delivering designs to market of increasing complexity quickly in 28nm is a technology treadmill for many SoC design teams. Even if the on-chip network requirements of prior designs were satisfied in-house, how far do these in-house products scale? Multiple companies provide on-chip network IP for varying interconnect solutions, and in general these offer designers varying capabilities for configurability, verification, architectural modeling and simulation.
So this is where the rubber meets the road and designers need to start asking the right questions to establish what works best for their products.
1) Is the on-chip network fast enough and will it allow my designs to scale for my platform roadmap that considers changing design requirements for performance, power and area? Recently, our market experiences include frequency highs of 1.6 GHz fabrics in 28nm HPM and 1 GHz fabrics in 28nm HPL, using only standard VT devices. For most mobile SoCs, this frequency headroom translates into much simpler timing convergence and enables fabric frequency vs. link width trade-offs to reduce routing challenges. For example, operating a long network link at 2x frequency allows about half of the wires and half as much storage where the link crosses domain boundaries.
2) How does the on-chip network help designers achieve their throughput requirements without massive routing congestion? As the network becomes deeper, the number of arbitration decisions increase and the likelihood that one data flow can block others grows. In addition to high frequency, the on-chip network needs both thread/virtual channel support to prevent shared links from blocking and powerful QoS systems that enable latency optimization for CPUs while providing guaranteed bandwidths to streaming cores. Without virtual channel support, meeting the DRAM throughput goals normally requires routing ten or more distinct links to the DRAM scheduler and large FIFOs at the IP cores.
3) How does placement of the IP cores on the SoC impact the on-chip network? SoC architects typically optimize the network and memory system long before the chip floorplan is known. IP core clustering that seemed logical from connectivity or coarse grained power management perspectives frequently does not match the floorplan-driven constraints. As a result, SoC integration and back end teams are left with a difficult choice: preserve the network topology and the associated performance modeling, but live with much longer network links that increase congestion and timing closure challenges, or change the network topology to match the floorplan and go back through the time consuming architecture optimization phase. Sonics’ new GHz NoC, SonicsGN, offers a third choice: change the physical topology to match the floorplan while leveraging QoS-aware virtual channels to protect the logical topology – and thus the previous performance analysis. Note that the resulting floorplan-optimized physical topology is then perfectly positioned for fine-grained power and clock domain partitioning.
When the SoC is done, there is an on-chip network connecting 100+ IP cores, multiple transactions to/from memory and other IP cores. Now designers need to ask: 4)Are all the IP components properly hooked up and completely functional? 5) How robust is the test bench and verification environment?
With over 1B units shipped by Sonics’ licensees, we see more differing types of IP cores than many semiconductor companies and understand the system challenges and tradeoffs. These experiences and processes, presented as standard IP products, leverage a larger R&D investment than most in-house alternatives and provide a higher reliability of integration to designers leveraging on-chip network IP.
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As I prepare to hit Barcelona for Mobile World Congress, I get the feeling that this will be a ‘do-over’ of last month’s CES, only without all the HD and 3D TVs. Although wireless infrastructure and applications are a big part of MWC, at the device level, tablets and smartphones will continue to dominate all the discussions. Déjà vu, anyone? Yet the reality is we are in the early generations of these products, and especially from the perspective of the underlying SoC technology, we are just starting to scratch the surface of this multi-dimensional tech discussion.
In last month’s blog, I looked at the critical role of the SoC as an enabling technology and how device manufacturers need a strong SoC strategy to stay relevant. I am in no way discounting the value that OEMs bring in differentiating their products at the device level (we have all come to know and love Apple). However, by taking responsibility for driving SoC architectures it will ensure that these OEMs will continue to differentiate with better features and at a lower cost, making all of us consumers happy.
So let’s review some of the SoC device and system requirements to determine what will be necessary to keep these mobile markets hot…and getting even hotter.
How fast is fast? The first and seemingly most interesting question is how fast does the SoC have to run? The real answer to the question is almost moot because the default answer is: The faster you can run, the better. Of course I understand that in mobile systems, speed and power consumption need to be intricately balanced. However, we are now—especially with the tablet architecture—at a speed inflection point of moving from single-core, 1GHz processors to multicore processors with up to 4 cores and even a 5th core for low-power running at speeds of 2GHz+.
I say the speed question is moot for several reasons. As the process technology shrinks (28nm and below), there is increased space on the die for more processors. This is not only true for the CPU, but the GPU is now rivaling the CPU in die area. Clearly device manufacturers want to take full advantage of all this processing power allowing for speed ‘margin’ in the design. This margin gives designers the peace of mind knowing that the SoC will have the longevity needed to keep up with all the latest and multi-tasking applications now prevalent in tablets and smart phones. And finally at a very practical level, having extra speed provides the SoC designer the margin needed to ensure that they can close timing at the target speed!
It really is all about bandwidth. Given the increased speed of the processors, we now need to look at how this will affect the rest of the system. The first and most obvious place to start is the memory subsystem. Without a properly designed memory subsystem, there will be no way to utilize all the available processing power. Wide I/O memory is emerging as one solution to the SoC bandwidth problem. Although Wide I/O memory is not without its manufacturing challenges, from an architectural perspective it offers the necessary increase in bandwidth by utilizing four channels (in the first generation) of DRAM memory. This increased bandwidth also comes with the advantage of having a lower-frequency memory interface, along with reduced power consumption, because the memory is connected directly to the SoC die using TSV technology.
To maintain bandwidth, it is also important to have a high-performance on-chip network that can support the high speed and connectivity requirements between the processors and memory. For example, with processors running at 2GHz, the network must be able to operate with margins at 1GHz to keep pace with the processors. It is vital for the network to support ‘load balancing’ of the traffic flowing to the four channels of memory to ensure maximum DRAM utilization.
It’s the total system. Without a doubt, the speed and memory performance are key components of an SoC that are helping to drive the technology forward. To move the technology and end-products to the next level, however, it will require a broader integration of not only the SoC hardware (the stage we are today), but also the integration of the SoC with the OS and applications. Of course this is easier said than done, given the limited number of companies that are vertically integrated. And even the ones that are don’t necessarily have the proper communications channels in place between hardware and software teams to effectively achieve this goal.
Looking at the SoC from the systems perspective offers the possibility of significantly optimizing applications performance and power management (for starters). We are now beginning to see application-aware operating systems, but we don’t see the link to the underlying hardware, which can offer a real breakthrough in overall system performance (AKA enhanced end-user experience).
The next level. There is clearly a lot of work to do at the SoC integration level to achieve the increased performance and bandwidth needed for the next generation of mobile devices. Keep in mind we didn’t even explore some of the custom features required for this market, such as security. The real challenge for moving the SoC platforms forward is to find the right catalyst to force teams—both hardware and software from the application level down to the lowest level hardware—to look at the problem from the total system perspective. And, fingers crossed, to finally stop focusing only on their piece of the problem.
This catalyst can emerge from a lead OEM moving the bar where all other companies will then have to oblige, or from a specific demand from the market—a new ‘must-have’ capability. Having a total systems view will allow for better coordination of hardware resources, giving the software team better access and visibility of the low-level hardware. Ultimately, setting up the triple threat demanded by consumers: Getting dramatically better performance with significantly lower power, translating to a superior user experience.
So when will we stop talking about SoC architectures for mobile devices? Perhaps when we retire…
–Frank Ferro is Director of Marketing at Sonics.
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Analysts agree that much of the semiconductor growth over the next few years will be in the mobile market segments—smart phones, tablets and ultra-books, in particular. At the recent CES, there was no lack of these devices on display, all which are competing to cash in on the cachet that Apple has developed around these products. Although ultra-books will eventually just be notebooks in their final form (I can’t wait to get rid of this heavy block I carry around), this thin, light, long battery life device will add new life and enthusiasm to the notebook PC market. This is a positive sign of the times and a welcome technological progression we all await.
It was also interesting to see how quickly companies, namely dominant players just one year ago in the mobile market, now struggle to simply remain relevant. This was clearly evident when wandering by the RIM and Nokia booths and seeing the lack of traffic in what was otherwise a jam-packed show floor (I could hardly move in most booths). In fairness, Nokia did have a lot of interest in its Lumia smart phone running Windows, but it felt like they were playing catch-up and not setting the pace as they once did. Other giants like Intel and Microsoft are now working to gain a foothold in the mobile market. Both have been largely unsuccessful up to this point, but are finally gaining some traction.
However, the most fascinating dynamic of the show for me was to see how much interest and traffic was driven by the semiconductor companies. The Qualcomm and NVIDIA booths, for example, were a constant mass of people and were demanding a lot of interest. Yes, this is somewhat satisfying as a long-time semiconductor person, but the reality is that chip companies and semiconductor technology are now the global drivers for the most popular CE devices.
So what is it that has generated so much intrigue in semiconductor companies? The answer, hands down, is SoCs. It has become clear that the companies that control the SoCs to a large degree control the platform for these hot mobile devices. As the system companies shed their semiconductor resources over the last few years, much of the knowledge base and control was given to the semiconductor companies. Is it any surprise that Apple reversed this trend and is becoming more vertically integrated with respect to processors? The numbers speak for themselves. In fact, in 2011 alone, Apple was the single largest chip buyer in the industry, surpassing Samsung and HP. The discussion now has turned to how fast the applications processors can go, how many cores they will have, how fast is the graphics processor, and will the baseband be integrated along with all the other radios? The discussion then quickly jumps to the process technology—will this be 28nm, or 22nm or 14nm?
Of course, IP companies are also a critical and essential part of the SoC discussion. IP companies, for their part, are making a “land-grab” by trying to control more of the silicon content by providing a systems solution as opposed to individual IP blocks. Clearly for device manufacturers to stay relevant they have to be able to execute a successful go-to market SoC strategy, which means dealing effectively with both silicon and IP companies that are central to the SoC. In order to differentiate products with new features that the consumers want—and to deliver ahead of or on schedule—it is critical to know how to get the most out of both the IP and silicon that is available. IP providers in particular are driving SoC innovation with processors, GPUs, DSPs and NoCs—to name only a few critical IP blocks.
As we’ve all seen since 2008, the market is unforgiving and the rapid descent of yesterday’s leaders in the market is unmistakable. There are no do-overs, so you better be right and aim high the first time—and hit your target. Most companies today, however, do not want to become, or at least can’t afford to be vertically integrated, but with well-managed relationships with IP vendors they can maintain an innovative edge in spite of that challenge. I think the companies that learn how to take advantage of the investments that are already being made in critical IP will remain relevant and perhaps even be part of the New Electronic World Order.
–Frank Ferro is Director of Marketing at Sonics.
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As I’m reading through year-end articles on the top technologies of 2011, along with predictions of what’s hot for 2012, I naturally start to reflect on the emerging technologies for the year ahead—and will anyone see them coming?
Undoubtedly this was another year where rapid technology adoption changed our behavior throughout the day. It was the year of the tablet, the smart phone, LTE and Android, to name just a few. It is hard to believe that the iPad2 came out less than one year ago and now tablets already have become a hot household product that spans generations throughout the home–small children, us middle-aged technology enthusiasts, and even our parents who were just struggling with e-mail downloads not too long ago. When my wife, the least tech-savvy person on the planet and proud, self-acclaimed late adopter, asked for one of her own, I knew we were on the cusp of a major consumer shift and the widespread humanization of technology. As we’ve all seen, tablets are omnipresent, across all ages, and have made their way far beyond the confines of business meetings.
But think back. Did anyone actually predict the success of the tablet? There were early rumblings in the late ’90s about “thin-client computers” and then its successor, the netbook, in 2009. Then Apple and Microsoft claimed the first concept tablets in early 2000s. And remember pen computing from the ’90s? Talk about flashbacks. And what about smart phones, MP3 players or any of the high-tech gadgets we can’t put down today? If history is an indicator of the future, then let’s take a look at some technologies that have paved the way for many of the products we can’t live without today. And in doing so, perhaps we can gain some insight as we look forward to 2012 and beyond.
Having worked as a DSP engineer and then in DSP marketing for AT&T/Lucent for many years, I’ve seen up close and personal many attempts to change the way we interact with high-tech gadgets (speech recognition, handwriting recognition, speech coding, audio coding.) These are some of the underlying technologies in the products we use today, but that is all they are—technology.
I can recall the launch of the AT&T EO personal communicator (GO OS), a handwriting recognition tablet PC released in the early ’90s. I was given one to use for evaluation and it was not bad, fairly fast (page turn speed was the metric then) with good handwriting recognition. The device was natural to use in meetings. It wasn’t nearly as obnoxious and socially unacceptable as typing on a laptop keyboard (at least it was unacceptable at that time). The device experienced some success in vertical markets, but it and devices like it failed overall in the marketplace. Why? Ultimately it was about cost, content and usability. Tablet PCs for all their popularity today are mostly ‘output’ devices. Even today, it is tough to input a lot of data via the tablet, so without wireless broadband and all the content on the Internet, the device becomes far from optimal very quickly.
Remember the PDA or the Palm Pilot? I’m pretty sure they were ultimately just expensive calendars.
Here are a few more examples of products and technologies that were way ahead of their time, or emerged in unexpected ways:
• POTS Video Phone: This ended as a quickly as it was released. The first real consumer incarnation is Skype for personal communications. And note that the video is rarely used for business calls. Do you really want to see your colleagues at their home late at night? Pass.
• Voice recognition: This is another technology that has been around for 30+ years with niche applications in financial services and the airlines industry. Can you imagine using this technology in today’s cubicle-based office? Everyone talking/yelling slowly and intentionally into their phones at the same time? Still waiting on the killer app…
• Wireless LAN: It was around for 10 years before Apple decided to put it in the PC, then everyone quickly followed.
• MP3 Players: These were finally made popular with the online music store (not technology).So what have we learned here? Technology never “sticks” the way we expect, and in fact, it is difficult to predict when, if and in what form a product will emerge successfully in the marketplace. As engineers, we tend to get excited about the technology and forget that products ultimately will be accepted by the consumer the second it doesn’t “feel” like a high-tech gadget, when you don’t need your own personal system administrator, and when it can be used to solve very practical problems and streamline behavior.
So applying some of these principles may help us to see what will succeed as we look into next year. Some of the hot technologies now include gesture recognition, 3D and NFC (near-field communications). NFC may be an easy one to predict because it already has seen some success in Japan and Europe, and is waiting for some major handset vendors to bring it to market in the coming months. NFC does, in fact, solve a practical problem for consumers to securely and easily pay for their purchases. NFC’s proliferation in the rest of the world, however, will depend on a use model that is acceptable for the consumer, along with embedded software and hardware that ensures they are 100% secure.
3D viewing may be a more interesting case. 3DTV has been slow to catch on because the “human” interaction model is not there yet. Wearing glasses and having to contort the body for the best viewing position are bad enough. But there’s also a more fundamental question: Do I want (or am I ready) to see things in 3D? Gesture recognition is even more forward-looking. This technology is widely depicted in various forms in movies and TV, and although you can see concepts of how the technology will be used, it is not clear what the first incarnation of products will be. Personally, I can’t see myself swinging my hands on an airplane when I barely have enough room to type on a keyboard as is! Again, fundamentally it has to solve a practical, real-world problem and cannot just be more technology for the sake of technology. Consumers don’t have the patience for that anymore.
Over the last decade, we have seen the most technologically advanced consumer devices come to life in our sector, with semiconductor technology powering these amazing innovations. As an IP provider, choosing the winning technologies, markets and customers is critical for our success because it’s our job to lay the fundamental groundwork for this very innovation. Providing critical IP, at the right time in the design cycle, will enable semiconductor leaders to do what they do best, namely focus on their specific value-add in solving problems at the consumer level.
This core IP includes better ways to develop high-speed silicon for SoC performance in the 1 to 2GHz range now required in tablets and smart phones. To make efficient use of all this processing power, IP is required to enable higher memory bandwidth technologies like multi-channel support for wide I/O, along with superior power management. These highly efficient, high-performance SoCs will provide the processing power for future technologies, such as gesture recognition, and those that have yet to even be imagined.
No doubt in 2012 we will see companies continue to push the underlying technology forward, creating innovation around the next generations of tablets and smart phones and that one new device that will be under your Christmas tree next year but only a twinkle in someone’s eye today.
Happy Holidays and best wishes for a successful 2012!
–Frank Ferro is Director of Marketing at Sonics.
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One of the major advances in SoC design methodologies more than a decade ago was the decoupling of the network-on-chip (NoC) from the individual IP cores throughout the SoC. This was (and is) accomplished through the use of carefully specified sockets such as OCP, the old VSIA VCI and (somewhat later) AMBA-AXI, which establish clear boundaries of communication responsibility and thereby enable independent development of IP cores.
The decoupling methodology, enabled by the network agents that isolate the cores from the network fabric, allows for the optimum provision of the local operating environment for each functional core to best meet that core’s basic communication needs (e.g. timing, protocol, data widths and addressing). It was a significant step in the introduction of Sonics’ NoC products.
These NoC products not only provide signal and protocol decoupling, which are now common to many NoC approaches, but also deliver performance layer decoupling. Performance decoupling enables better isolation of traffic flows through the network, with sophisticated quality-of-service management through the use of virtual channels (threads) and strategically positioned buffering within the network.
Sonics’ CTO, Drew Wingard, wrote a chapter in the book “Interconnect-Centric Design for Advanced NoCs and SoCs” about the various forms of decoupling that we believe are essential elements of advanced SoC platform design methodologies. When combined, these decoupling approaches enable rapid integration of arbitrary collections of IP cores and subsystems with high confidence in the correctness, functionality and performance of the resulting communication architecture.
Decoupling also enables us to introduce entirely new generations of NoC fabrics that can immediately leverage all of our customers’ existing IP assets.
Previous Sonics’ blogs have covered the value of decoupling as it relates to concurrent data flow, but now let’s look at a new, significant aspect of decoupling that is becoming increasingly vital to SoC designers—decoupling of power and clocking domains. As the former CTO of Silistix, a company that was founded on the concept of clock decoupling for NoCs, I am excited to see this technology truly come of age and mature right as customers are demanding more novel methodologies for sophisticated power management in next-generation SoC designs.
As SoC designers strive for lower power consumption, the number of clock and power domains continues to increase. These domains enable power reduction by switching off local supplies to eliminate leakage current, dynamically scaling voltages and clocks (especially in processing subsystems such as CPUs, GPUs and video engines) to optimize active power for operating conditions and altering IP core clocks to meet the needs of application usage scenarios. This increase in domains is also a function of the increase in the number of heterogeneous cores that are present in the SoC, which drives the need to provide Globally Asynchronous Locally Synchronous (GALS) networks that speed timing closure.
A properly architected network-on-chip needs to be able to deal natively with each of these domains, meaning flexible domain crossing choices, zero performance loss at a crossing, and importantly, allowing power-boundaries to be positioned anywhere within the network. Having the ability to partition the SoC into many fine-grained, separately controlled domains, enables the SoC designer to tune each IP core or subsystem to minimize energy consumption. That enables new levels of power control. Aggressive power management is, without a doubt, a key differentiator in this mobile device-crazed market.
So having the ability to effectively decouple the system has become critical to many aspects of advanced SoC development, including having a much more robust design methodology and superior system performance by allowing more data flow concurrency—and now, superior power management. On the surface, decoupling may sound like an esoteric concept, but ultimately may be a secret weapon for SoC design.
–John Bainbridge is a technologist in the office of the CTO at Sonics.
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Designers in the consumer electronics market—mobile in particular—are constantly looking for new ways to reduce cost and power while increasing performance. This is far from novel. With consumers’ unrelenting demand for more features at lower prices, you would think semiconductor companies would jump when confronted with a technology that gives them a real competitive edge. The technology I’m referring to is embedded DRAM (eDRAM). I know you may be thinking the cost is prohibitive and this would offset any potential benefit. Hold that thought.
Before we get to cost, let’s first look at the SoC architecture and how the memory subsystem plays a key role in the overall efficiency of the SoC. I say efficiency because with distributed heterogeneous architectures, if careful consideration is not given to the memory subsystem then it will impact many aspects of the chip, especially performance and power. A couple of brief examples may convince you:
- The memory subsystem affects performance: This one should be the most obvious, given that if requests from the various processors are not serviced quickly due to high latency, the applications performance will suffer (i.e. you wait).
- The memory subsystem affects power and cost: When requests are not serviced quickly the processor cores have to spend more time in active mode consuming more power. The problem only gets worse as you try to overcome performance issues with techniques such as increasing the chip frequency or increasing buffer sizes to allow more requests to be handled—because these both add power and cost to the system. Even adding a second CPU core may be the solution, but again this increases the cost and power.
So what do SoC designers need in order to improve the efficiency of DRAM subsystems? The answer is to minimize read latency and increase memory bandwidth (note that this is the primary function of the cache). The frustrating thing for embedded SoC developers, however, is that what they get from DRAM manufacturers is higher-density DRAMs with no improvements in latency. DRAM vendors keep marching down the path they understand, namely more density with each generation. They have reluctantly moved to newer specs that increase I/O bandwidth, but these specs are hard to use—relying for example on accesses in larger chunks than processors may need. As long as the server market, which requires density, provides the majority of the demand, there is insufficient motivation for the DRAM vendors to optimize for what the mobile market really needs—lower latency.
As an alternative to using external DRAM, developers should now consider using embedded DRAM. eDRAM can be used either in combination with, or sometimes as a total replacement for external DRAM. In many cases, this is more effective than trying to make use of DRAM that was designed primarily for the computing market. eDRAM has the potential to radically improve latency and bandwidth, thereby improving the overall SoC performance while reducing power. Simulations of embedded systems using eDRAM show about 2.5x to 4x improvement in MIPS when compared to the same processor using external DRAM. These simulations also show that using eDRAM allows more system performance than adding a second processor! That’s right, one processor plus eDRAM has higher performance than two processors with external DRAM. Even the power showed significant improvement with external DRAM consuming 2x to 5x more power than eDRAM (while not even including the power consumption of the PHY).
Given so much potential, what’s the hold up? Unfortunately, eDRAM is largely misunderstood by many SoC developers. There are several different technologies used for eDRAM. The best known uses trench capacitors for the storage. This requires a special and expensive process, and is most widely available in SOI, so most people think of eDRAM as expensive. But there are other eDRAM technologies that use metal-insulator-metal stack capacitors for the storage. These have few or no special process steps, are almost as dense, work on bulk CMOS, and only cost a little more than plain vanilla CMOS. For these reasons, I really think developers are missing a big opportunity by passing on eDRAM.
I understand that simulation results and actual chip results are not the same. But with so much potential—one processor doing the job better than two with 1/5 of the power—it seems like a no-brainer to at least do some further investigation.
- Steve Hamilton is an applications architect at Sonics.
System-Level Design recently interviewed Sonics CEO, Grant Pierce, about the future SoC design.
