Sonics, Inc. - The Official Blog

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Analysts agree that much of the semiconductor growth over the next few years will be in the mobile market segments—smart phones, tablets and ultra-books, in particular. At the recent CES, there was no lack of these devices on display, all which are competing to cash in on the cachet that Apple has developed around these products. Although ultra-books will eventually just be notebooks in their final form (I can’t wait to get rid of this heavy block I carry around), this thin, light, long battery life device will add new life and enthusiasm to the notebook PC market. This is a positive sign of the times and a welcome technological progression we all await.

It was also interesting to see how quickly companies, namely dominant players just one year ago in the mobile market, now struggle to simply remain relevant. This was clearly evident when wandering by the RIM and Nokia booths and seeing the lack of traffic in what was otherwise a jam-packed show floor (I could hardly move in most booths). In fairness, Nokia did have a lot of interest in its Lumia smart phone running Windows, but it felt like they were playing catch-up and not setting the pace as they once did. Other giants like Intel and Microsoft are now working to gain a foothold in the mobile market. Both have been largely unsuccessful up to this point, but are finally gaining some traction.

However, the most fascinating dynamic of the show for me was to see how much interest and traffic was driven by the semiconductor companies. The Qualcomm and NVIDIA booths, for example, were a constant mass of people and were demanding a lot of interest. Yes, this is somewhat satisfying as a long-time semiconductor person, but the reality is that chip companies and semiconductor technology are now the global drivers for the most popular CE devices.

So what is it that has generated so much intrigue in semiconductor companies? The answer, hands down, is SoCs. It has become clear that the companies that control the SoCs to a large degree control the platform for these hot mobile devices. As the system companies shed their semiconductor resources over the last few years, much of the knowledge base and control was given to the semiconductor companies. Is it any surprise that Apple reversed this trend and is becoming more vertically integrated with respect to processors? The numbers speak for themselves. In fact, in 2011 alone, Apple was the single largest chip buyer in the industry, surpassing Samsung and HP. The discussion now has turned to how fast the applications processors can go, how many cores they will have, how fast is the graphics processor, and will the baseband be integrated along with all the other radios? The discussion then quickly jumps to the process technology—will this be 28nm, or 22nm or 14nm?

Of course, IP companies are also a critical and essential part of the SoC discussion. IP companies, for their part, are making a “land-grab” by trying to control more of the silicon content by providing a systems solution as opposed to individual IP blocks. Clearly for device manufacturers to stay relevant they have to be able to execute a successful go-to market SoC strategy, which means dealing effectively with both silicon and IP companies that are central to the SoC. In order to differentiate products with new features that the consumers want—and to deliver ahead of or on schedule—it is critical to know how to get the most out of both the IP and silicon that is available. IP providers in particular are driving SoC innovation with processors, GPUs, DSPs and NoCs—to name only a few critical IP blocks.

As we’ve all seen since 2008, the market is unforgiving and the rapid descent of yesterday’s leaders in the market is unmistakable. There are no do-overs, so you better be right and aim high the first time—and hit your target. Most companies today, however, do not want to become, or at least can’t afford to be vertically integrated, but with well-managed relationships with IP vendors they can maintain an innovative edge in spite of that challenge. I think the companies that learn how to take advantage of the investments that are already being made in critical IP will remain relevant and perhaps even be part of the New Electronic World Order.

–Frank Ferro is Director of Marketing at Sonics.

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As I’m reading through year-end articles on the top technologies of 2011, along with predictions of what’s hot for 2012, I naturally start to reflect on the emerging technologies for the year ahead—and will anyone see them coming?

Undoubtedly this was another year where rapid technology adoption changed our behavior throughout the day. It was the year of the tablet, the smart phone, LTE and Android, to name just a few. It is hard to believe that the iPad2 came out less than one year ago and now tablets already have become a hot household product that spans generations throughout the home–small children, us middle-aged technology enthusiasts, and even our parents who were just struggling with e-mail downloads not too long ago. When my wife, the least tech-savvy person on the planet and proud, self-acclaimed late adopter, asked for one of her own, I knew we were on the cusp of a major consumer shift and the widespread humanization of technology. As we’ve all seen, tablets are omnipresent, across all ages, and have made their way far beyond the confines of business meetings.

But think back. Did anyone actually predict the success of the tablet? There were early rumblings in the late ’90s about “thin-client computers” and then its successor, the netbook, in 2009. Then Apple and Microsoft claimed the first concept tablets in early 2000s. And remember pen computing from the ’90s? Talk about flashbacks. And what about smart phones, MP3 players or any of the high-tech gadgets we can’t put down today? If history is an indicator of the future, then let’s take a look at some technologies that have paved the way for many of the products we can’t live without today. And in doing so, perhaps we can gain some insight as we look forward to 2012 and beyond.

Having worked as a DSP engineer and then in DSP marketing for AT&T/Lucent for many years, I’ve seen up close and personal many attempts to change the way we interact with high-tech gadgets (speech recognition, handwriting recognition, speech coding, audio coding.) These are some of the underlying technologies in the products we use today, but that is all they are—technology.

I can recall the launch of the AT&T EO personal communicator (GO OS), a handwriting recognition tablet PC released in the early ’90s. I was given one to use for evaluation and it was not bad, fairly fast (page turn speed was the metric then) with good handwriting recognition. The device was natural to use in meetings. It wasn’t nearly as obnoxious and socially unacceptable as typing on a laptop keyboard (at least it was unacceptable at that time). The device experienced some success in vertical markets, but it and devices like it failed overall in the marketplace. Why? Ultimately it was about cost, content and usability. Tablet PCs for all their popularity today are mostly ‘output’ devices. Even today, it is tough to input a lot of data via the tablet, so without wireless broadband and all the content on the Internet, the device becomes far from optimal very quickly.

Remember the PDA or the Palm Pilot? I’m pretty sure they were ultimately just expensive calendars.

Here are a few more examples of products and technologies that were way ahead of their time, or emerged in unexpected ways:

• POTS Video Phone: This ended as a quickly as it was released. The first real consumer incarnation is Skype for personal communications. And note that the video is rarely used for business calls. Do you really want to see your colleagues at their home late at night? Pass.
• Voice recognition: This is another technology that has been around for 30+ years with niche applications in financial services and the airlines industry. Can you imagine using this technology in today’s cubicle-based office? Everyone talking/yelling slowly and intentionally into their phones at the same time? Still waiting on the killer app…
• Wireless LAN: It was around for 10 years before Apple decided to put it in the PC, then everyone quickly followed.
• MP3 Players: These were finally made popular with the online music store (not technology).

So what have we learned here? Technology never “sticks” the way we expect, and in fact, it is difficult to predict when, if and in what form a product will emerge successfully in the marketplace. As engineers, we tend to get excited about the technology and forget that products ultimately will be accepted by the consumer the second it doesn’t “feel” like a high-tech gadget, when you don’t need your own personal system administrator, and when it can be used to solve very practical problems and streamline behavior.

So applying some of these principles may help us to see what will succeed as we look into next year. Some of the hot technologies now include gesture recognition, 3D and NFC (near-field communications). NFC may be an easy one to predict because it already has seen some success in Japan and Europe, and is waiting for some major handset vendors to bring it to market in the coming months. NFC does, in fact, solve a practical problem for consumers to securely and easily pay for their purchases. NFC’s proliferation in the rest of the world, however, will depend on a use model that is acceptable for the consumer, along with embedded software and hardware that ensures they are 100% secure.

3D viewing may be a more interesting case. 3DTV has been slow to catch on because the “human” interaction model is not there yet. Wearing glasses and having to contort the body for the best viewing position are bad enough. But there’s also a more fundamental question: Do I want (or am I ready) to see things in 3D? Gesture recognition is even more forward-looking. This technology is widely depicted in various forms in movies and TV, and although you can see concepts of how the technology will be used, it is not clear what the first incarnation of products will be. Personally, I can’t see myself swinging my hands on an airplane when I barely have enough room to type on a keyboard as is! Again, fundamentally it has to solve a practical, real-world problem and cannot just be more technology for the sake of technology. Consumers don’t have the patience for that anymore.

Over the last decade, we have seen the most technologically advanced consumer devices come to life in our sector, with semiconductor technology powering these amazing innovations. As an IP provider, choosing the winning technologies, markets and customers is critical for our success because it’s our job to lay the fundamental groundwork for this very innovation. Providing critical IP, at the right time in the design cycle, will enable semiconductor leaders to do what they do best, namely focus on their specific value-add in solving problems at the consumer level.

This core IP includes better ways to develop high-speed silicon for SoC performance in the 1 to 2GHz range now required in tablets and smart phones. To make efficient use of all this processing power, IP is required to enable higher memory bandwidth technologies like multi-channel support for wide I/O, along with superior power management. These highly efficient, high-performance SoCs will provide the processing power for future technologies, such as gesture recognition, and those that have yet to even be imagined.

No doubt in 2012 we will see companies continue to push the underlying technology forward, creating innovation around the next generations of tablets and smart phones and that one new device that will be under your Christmas tree next year but only a twinkle in someone’s eye today.

Happy Holidays and best wishes for a successful 2012!

–Frank Ferro is Director of Marketing at Sonics.

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One of the major advances in SoC design methodologies more than a decade ago was the decoupling of the network-on-chip (NoC) from the individual IP cores throughout the SoC. This was (and is) accomplished through the use of carefully specified sockets such as OCP, the old VSIA VCI and (somewhat later) AMBA-AXI, which establish clear boundaries of communication responsibility and thereby enable independent development of IP cores.

The decoupling methodology, enabled by the network agents that isolate the cores from the network fabric, allows for the optimum provision of the local operating environment for each functional core to best meet that core’s basic communication needs (e.g. timing, protocol, data widths and addressing). It was a significant step in the introduction of Sonics’ NoC products.

These NoC products not only provide signal and protocol decoupling, which are now common to many NoC approaches, but also deliver performance layer decoupling. Performance decoupling enables better isolation of traffic flows through the network, with sophisticated quality-of-service management through the use of virtual channels (threads) and strategically positioned buffering within the network.

Sonics’ CTO, Drew Wingard, wrote a chapter in the book “Interconnect-Centric Design for Advanced NoCs and SoCs” about the various forms of decoupling that we believe are essential elements of advanced SoC platform design methodologies. When combined, these decoupling approaches enable rapid integration of arbitrary collections of IP cores and subsystems with high confidence in the correctness, functionality and performance of the resulting communication architecture.

Decoupling also enables us to introduce entirely new generations of NoC fabrics that can immediately leverage all of our customers’ existing IP assets.

Previous Sonics’ blogs have covered the value of decoupling as it relates to concurrent data flow, but now let’s look at a new, significant aspect of decoupling that is becoming increasingly vital to SoC designers—decoupling of power and clocking domains. As the former CTO of Silistix, a company that was founded on the concept of clock decoupling for NoCs, I am excited to see this technology truly come of age and mature right as customers are demanding more novel methodologies for sophisticated power management in next-generation SoC designs.

As SoC designers strive for lower power consumption, the number of clock and power domains continues to increase. These domains enable power reduction by switching off local supplies to eliminate leakage current, dynamically scaling voltages and clocks (especially in processing subsystems such as CPUs, GPUs and video engines) to optimize active power for operating conditions and altering IP core clocks to meet the needs of application usage scenarios. This increase in domains is also a function of the increase in the number of heterogeneous cores that are present in the SoC, which drives the need to provide Globally Asynchronous Locally Synchronous (GALS) networks that speed timing closure.

A properly architected network-on-chip needs to be able to deal natively with each of these domains, meaning flexible domain crossing choices, zero performance loss at a crossing, and importantly, allowing power-boundaries to be positioned anywhere within the network. Having the ability to partition the SoC into many fine-grained, separately controlled domains, enables the SoC designer to tune each IP core or subsystem to minimize energy consumption. That enables new levels of power control. Aggressive power management is, without a doubt, a key differentiator in this mobile device-crazed market.

So having the ability to effectively decouple the system has become critical to many aspects of advanced SoC development, including having a much more robust design methodology and superior system performance by allowing more data flow concurrency—and now, superior power management. On the surface, decoupling may sound like an esoteric concept, but ultimately may be a secret weapon for SoC design.

–John Bainbridge is a technologist in the office of the CTO at Sonics.

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Designers in the consumer electronics market—mobile in particular—are constantly looking for new ways to reduce cost and power while increasing performance. This is far from novel. With consumers’ unrelenting demand for more features at lower prices, you would think semiconductor companies would jump when confronted with a technology that gives them a real competitive edge. The technology I’m referring to is embedded DRAM (eDRAM). I know you may be thinking the cost is prohibitive and this would offset any potential benefit. Hold that thought.

Before we get to cost, let’s first look at the SoC architecture and how the memory subsystem plays a key role in the overall efficiency of the SoC. I say efficiency because with distributed heterogeneous architectures, if careful consideration is not given to the memory subsystem then it will impact many aspects of the chip, especially performance and power. A couple of brief examples may convince you:

1. The memory subsystem affects performance: This one should be the most obvious, given that if requests from the various processors are not serviced quickly due to high latency, the applications performance will suffer (i.e. you wait).
2. The memory subsystem affects power and cost: When requests are not serviced quickly the processor cores have to spend more time in active mode consuming more power. The problem only gets worse as you try to overcome performance issues with techniques such as increasing the chip frequency or increasing buffer sizes to allow more requests to be handled—because these both add power and cost to the system. Even adding a second CPU core may be the solution, but again this increases the cost and power.

So what do SoC designers need in order to improve the efficiency of DRAM subsystems? The answer is to minimize read latency and increase memory bandwidth (note that this is the primary function of the cache). The frustrating thing for embedded SoC developers, however, is that what they get from DRAM manufacturers is higher-density DRAMs with no improvements in latency. DRAM vendors keep marching down the path they understand, namely more density with each generation. They have reluctantly moved to newer specs that increase I/O bandwidth, but these specs are hard to use—relying for example on accesses in larger chunks than processors may need. As long as the server market, which requires density, provides the majority of the demand, there is insufficient motivation for the DRAM vendors to optimize for what the mobile market really needs—lower latency.

As an alternative to using external DRAM, developers should now consider using embedded DRAM. eDRAM can be used either in combination with, or sometimes as a total replacement for external DRAM. In many cases, this is more effective than trying to make use of DRAM that was designed primarily for the computing market. eDRAM has the potential to radically improve latency and bandwidth, thereby improving the overall SoC performance while reducing power. Simulations of embedded systems using eDRAM show about 2.5x to 4x improvement in MIPS when compared to the same processor using external DRAM. These simulations also show that using eDRAM allows more system performance than adding a second processor! That’s right, one processor plus eDRAM has higher performance than two processors with external DRAM. Even the power showed significant improvement with external DRAM consuming 2x to 5x more power than eDRAM (while not even including the power consumption of the PHY).

Given so much potential, what’s the hold up? Unfortunately, eDRAM is largely misunderstood by many SoC developers. There are several different technologies used for eDRAM. The best known uses trench capacitors for the storage. This requires a special and expensive process, and is most widely available in SOI, so most people think of eDRAM as expensive. But there are other eDRAM technologies that use metal-insulator-metal stack capacitors for the storage. These have few or no special process steps, are almost as dense, work on bulk CMOS, and only cost a little more than plain vanilla CMOS. For these reasons, I really think developers are missing a big opportunity by passing on eDRAM.

I understand that simulation results and actual chip results are not the same. But with so much potential—one processor doing the job better than two with 1/5 of the power—it seems like a no-brainer to at least do some further investigation.

- Steve Hamilton is an applications architect at Sonics.

System-Level Design recently interviewed Sonics CEO, Grant Pierce, about the future SoC design.

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By now it’s safe to say that complex, high-speed design is no longer a riddle….at least in theory.

We all know the end game. In its most fundamental form, isn’t it really a designer’s negotiation and compromise with the end user that comes down to action and reaction? We know users demand more and more applications to run simultaneously on their smart devices. We know that the underlying SoC in every device must sufficiently accommodate multiple data streams for each unique application. This is driving key architectural decisions for multi-core, multi-processor SoCs. Given that, how do we limit the amount of ‘compromise’ by the designer and give the customer more of that they want?

Having the ability to build an efficient, high-performance “network” is a critical part of the overall SoC architecture decision—ensuring that traffic volume, i.e. requests from multiple processor cores including the CPU, GPU, DSP and video processor, are given the adequate bandwidth. To design an optimal system, the network must first be able to handle the speed of the processors and DRAM. In addition, it must efficiently manage the data flow in order to manage concurrent processes.

With processor speeds climbing, having a network-on-chip (NoC) that can support GHz speeds has now moved beyond optional to essential as processors—even for mobile applications—are starting to approach or even surpass 2GHz. This high-speed network allows the processor to maximize performance and provides the SoC designer with the extra headroom needed as new functions are added and as processor speeds increase.

There is no disputing that the NoC speed is critical to meet SoC connectivity requirements. But the NoC must now go even further to ensure the maximum number of concurrent processes can be supported in order to provide the best user experience at the application level. A network that combines the highest frequency and advanced concurrency support will enable SoC designers to run multiple, high-speed applications simultaneously, which is the price of admission for today’s smart devices. At the end of the day, designers need to efficiently manage all their essential application concurrency to keep pace with the increased capabilities demanded by consumers.

So what are some of the ways that the network can support concurrent processes? One method is to design a network that has more spatially concurrent data paths. This is analogous to adding more lanes to a highway to eliminate any potential bottlenecks and increase traffic flow. The advantage of having more lanes is that it will provide predictable service at peak traffic times. The disadvantage, however, is that the system may be over-provisioned, wasting chip area and power during times when the bandwidth is not needed.

A more efficient solution is to design a system that takes advantage of the fact that 100% peak bandwidth utilization is not always needed. Staying with the highway analogy, think of those roads that change the direction of the lanes depending on the time of day. The concept of using “virtual” channels is similar. A virtual channel takes advantage of the fact that all resources in the system are not always utilized. With proper flow control, forward progress can be guaranteed for a unique data stream even over a shared resource. The result of using virtual channels is optimal system performance, while saving chip area because buffers and wires can be shared. Given the pressure on cost and power, the ability to save gates and wires while meeting the system performance is critical for success.

Another advantage of virtual channels with advanced flow control is that it has non-blocking properties. This means that traffic is never “blocked” from entering the network. Using just one more traffic analogy, a typical network will “meter” data flowing into the network like traffic lights at the highway on-ramps at rush hour. You have to wait and there will be a delay. With the non-blocking flow, control data is always permitted to enter the network and make progress, therefore maximizing the overall system concurrency.

Clearly designers are concerned with the SoC performance as it relates to the end application. To give the end-user more application concurrency, it is imperative to choose your on-chip network architecture carefully. Having a high-speed NoC is an important component in the overall network-on-chip design, allowing high-speed data to be moved to the various subsystem components in the network. You also must be sure that the network can deal efficiently with multiple data streams and not “block” traffic flow into the network, which is what other NoCs do today.

So if designers want to get in the fast lane or pass their competitors on the left, they will need a high-performance NoC with an architecture that supports a high degree of concurrency as a key component in the overall system design.

–Frank Ferro is Director of Marketing at Sonics.

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Normally summer is a time where most people slow down, relax, take vacations and the pace slows down accordingly with the seasonal ebb and flow of our industry. But not this summer.

Exhibit A, B, C, D and so on: This past month has demonstrated the profound element of change. Mostly in our wallets. The stock market volatility and global economic disruptions have echoed (and roared) around the world. We’ve seen the lowest 30-year mortgage rates, U.S. downgrades, company downsizing. Sure rollercoasters are often associated with summer, but not this kind. We are seeing rollercoasters of an entirely different persuasion altogether. In tech, Apple and Exxon Mobile have tag-teamed back and forth as the most valuable publically traded corporation. A lot of movement—nothing is still and quiet this summer. However, we all have been here before and are getting accustomed to the bumpy ride. And we know all too well to keep our chin up as bumpy rides and volatility breeds new opportunity!

So business goes on, IPOs are happening, new products are popping up left and right, and the cycle continues. There are still high expectations for strong technology companies to deliver and innovate, as more content is demanded (and shared) across connected communities worldwide. History has shown that the most successful companies thrive and innovate in a downturn…so we assume the position and carry on.

Look at one of the critical and most dominant market drivers today– the proliferation of video content. Consumers want video and they are choosing the solutions that are easiest to use with the richest variety of content. Nowhere is this more obvious than in Netflix’s recent business model change to separate its streaming offering from the snail-mail delivery of DVD content. The Netflix business model enables consumers to view content on a broad range of devices and form factors—and is banking on the fact that is what you want in 2011 and beyond. And we do.

All around us, digital video is migrating to tablets and smart phones, and the future digital TV/video consumption will shift from PCs to tablets. In fact, this week In-Stat said 65% of the U.S. population will own a smart phone and/or tablet by 2015. That amounts to more than 200 million people. This powerful statistic alone will dictate market activities and product priorities by almost all the semiconductor leaders—in every region.

Content is the basic driver for many system companies as they work to show alternatives to Apple’s strong ecosystem around a range of “iDevice” products that allow consumers “the content they want, when and where they want. ” With Apple’s rise in smart phones, its strong product offering has resulted in the company receiving 50% of the profits in the smartphone market and defining a new market (again) with tablets. That’s innovation my friends!

Earlier this year (Feb 2011), Cisco shared a comprehensive study on mobility and content and the effects on overall bandwidth consumption. For example, smart phones represent 13% of total global handsets in use today, but represent of 78% of traffic. And the tablets, a new category, are using five times the traffic of the average smart phone.

Consider that HP’s WebOS tablet didn’t show the volume traction to deliver significant results to HP, and HP quickly opted out and moved on to other strategies. Google’s acquisition of Motorola Mobility is seen to offer Google a war chest of patents while enabling Google’s Android vision to be accelerated with tighter control and earlier market entry of flagship devices. Apple, Intel and ARM are companies at the heart of others’ strategies in the quest to build compelling devices that win consumers and brand loyalty— while differentiating from their competitors.

So for the semiconductor architects, getting the right video performance and battery life is just as important as tuning for best processor performance. And today’s multicore devices are continuing to increase in complexity as more cores are used to explore different SoC results. Performance, battery life and cost efficiencies are the key attributes as SoC designers work to leverage similar IP cores and foundry nodes while differentiating products.

–Jack Browne is Senior Vice President of Sales and Marketing at Sonics.

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As an I IP provider, I have been watching with great interest the patent battles taking place between the major players in the wireless market. The now seemingly daily announcements of new lawsuits in the mobile consumer market translate to several things—wireless devices have become true consumer items, the dollars are high and new companies have reshaped the market landscape.

When I was selling wireless baseband chipsets, the first (and $64,000) question asked by the companies (to remain nameless) trying to establish themselves in the wireless market was, “Will you indemnify us?” Clearly they all knew that this day would come when the incumbent players were challenged to the point of asserting their patents. And they should. They have years of investment in these technologies and their property has to be protected. Asserting basic patents are undoubtedly a way to get paid, but what companies really want is total market dominance.

Today, the answer for “dominating” (from a technology perspective) often comes down to system performance in order to give the user the best experience—performance typically means adding more processor cores. The challenge has always been, however, how to utilize all the processors effectively to gain the maximum performance increase. If we look at the real system performance problem it usually boils down to DRAM access. Regardless of how many processors you have in the system, the memory is the choke point. Most of the system traffic has to access DRAM, and any inefficiency in the memory subsystem will affect the overall system performance (i.e. the number of applications that can run effectively), power and cost.

To solve these challenges, there are several areas of IP investments in the memory subsystem emerging today, including embedded DRAM, Wide I/O and TSV technology). To complement these silicon improvements, there is also an effort to improve quality of service algorithms (QoS), non-blocking network flow control, memory scheduling and interleaved memory access technology (IMT). These are the key components that will be necessary to take full advantage of the today’s and tomorrow’s new memory technologies.

Let’s consider first the effect of using embedded DRAM. This long promised technology has clear system performance and power advantages. Not having to access external DRAM saves significant power (all those pins gone and no PHY) and increases performance for the same reasons. When you layer on top of these performance gains better flow control algorithms, the net system improvements can be more efficient than adding a second processor core! The use of wide I/O DRAM will have a similar effect by opening up the DRAM bottleneck. Having fast access to multiple banks of DRAM with efficient load balancing technology (such as IMT) will provide the step function in performance needed to drive true product innovation.

As products commoditize, it becomes increasingly difficult for companies to differentiate. The user interface and underlying chipsets can only be so “unique” from the consumer perspective (hence the emergence of most patent battles). Although the product paradigm is established for now, innovation in the memory subsystem will be a key element in overall technology innovation to move the products forward and for the establishment of entirely new product paradigms.

With the stakes so high in the mobile market, I expect that the fight for market share will continue using all means available. How this plays out will be interesting to watch, too. But one thing is clear: The companies that take full advantage of these shifts in the underlying SoC IP will be the ones that stay on top—or else suffer the way that some of the incumbent players have, namely a slow, painful death.

–Frank Ferro is Director of Marketing at Sonics.

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Software is never-ending, or so the axiom goes. It shouldn’t take long to convince anyone that has used an electronic device of the truth of this statement. The PC environment is the most obvious (and obnoxious) example with daily application software updates, at the most inconvenient times, coupled with regularly scheduled updates for the OS. Even embedded devices like media players and cell phones need periodic updates.

As a former product manager responsible for delivering WLAN chipsets, one of the biggest challenges we had was delivering software drivers. Even when the hardware was finished, we would have to do frequent driver releases. Bugs were not the only reasons for new releases. Driver releases were also needed to accommodate all the permutations of operating systems, chips sets and customer applications. If someone had said me at that time that a change in the hardware could reduce the driver effort by even a small percentage, I would have paid very close attention.

Improving software efficiency is even more important in today’s competitive SoC market where performance, cost and TTM are critical to achieve success. The ability to reuse software, however, is often at odds with the rapid expansion of the hardware. Hardware teams rightfully leverage new process technologies, adding as much functionality into the chip as possible. The expansion of the hardware is often done with little or no regard to how it will impact existing software.

So the question becomes: Is it time for a new SoC model? It may seem counter-intuitive to think custom hardware can make software portable. Yet this is exactly what needs to be done to maximize system performance, and at the same time, reduce the burden on the software team.

Let’s look at a video SoC architecture to illustrate this concept. Hardware designers often separate the DRAM into two or more channels to maximize the overall system performance and DRAM access efficiency. To do this, one set of hardware processors will access one channel of DRAM while another set of processors access the second DRAM bank. This ensures that the traffic load in the system is balanced over the DRAM banks. The problem for the software team starts when a change is made to the chip, either by adding another bank of DRAM or more processors, or both. The previously written software will no longer work on the new chip because the system has been re-partitioned to accommodate the new processors, along with the repartitioning of the memory banks.

Taking a slightly different approach to the SoC architecture could have avoided this problem. If dedicated memory “load-balancing” hardware was added to the on-chip network of the SoC, the overall system performance could have been maintained while allowing software portability. With the on-chip network load-balancing the traffic flowing to memory, there is no longer a need for the hardware team to partition specific processors to dedicated banks of DRAM. Since traffic balancing is now done automatically, any processor in the system can access any bank of memory. The load-balancing hardware has the effect of making the memory access “virtual” relative to the software. In this case, the hardware actually makes the software portable!

With software resources accounting for an increasingly larger percentage of the overall chip cost (which chip companies rarely, if ever, get paid for), this approach to SoC design offers the benefit of abstracting the software from the hardware without losing control of the hardware. The concept in the above example is not only applicable to memory access, but a similar concept can be applied to power management (see my last blog), security and other critical system functions.

As more and more hardware blocks are modified to be “virtual,” then the reduction in software effort will be significant—resulting in improved SoC system performance—critical to success in today’s competitive SoC market. The statement “software is never-ending” is likely to remain true, but with some forethought in the overall system architecture, great strides can be made to improve software efficiency and reduce cost.

–Frank Ferro is Director of Marketing at Sonics.

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How many of us would go back to watching television in black and white, or carry around a 10-pound laptop or cell phone that resembles the ones in original brick form? For most consumers, it would even be hard to turn back the clock on more recent innovations like Wi-Fi and digital cameras (finding a place to plug-in the lap, run wires through the house, carrying around film! File that under U-G-H!!

But we as consumers don’t seem to mind reverting to the early days of cell phones to have the latest smart phone features. What aspect of this reversion, you ask? The Big “B”—battery life. Remember your first analog phone that had a half-day’s worth of battery life? To solve this problem, major cell phone companies demanded that your baseband chips support 170 hours of battery life (about one week) in standby mode and about five to seven hours of talk time. The good news was that these talk and standby times were actually achieved! Basic feature phones will easily last a week in standby mode.

But today I feel like I am back to the early days of cell phones. I need to charge the phone every day and constantly watch the power meter. There’s even a new twist. I need to turn off applications that reduce my battery life. File that under high maintenance. However, I will say, that standby time in some smart phones is not too bad—two to three days, providing you don’t use them!

So with all this talk about “power-aware” designs, where’s the progress? Clearly the need to have big touch screen displays with at least three radios in your phone (cellular, Wi-Fi, Bluetooth) is outpacing power-efficient designs. And then add the fact that leakage current gets worse as SoCs move to smaller process nodes, putting more strain on standby current. In addition, with smaller process nodes (45nm and 28nm) the power density increases, causing the need for more power and voltage domains on chip (that need to be controlled) in order to lower the average power of the SoC. So, how can we get ahead of this power curve (no pun intended) and get back to one-week standby times?

To truly create power-aware designs it will take a combination of system-architecture design, EDA tools, software and IP. Part of the challenge is that there is typically no one person on the design team responsible for power. Each piece of the system is doing its best to conserve power, but this, if not viewed from the system level, can hurt power consumption because what appears to be saving power in one domain is actually increasing the power in another. (I presented a paper demonstrating this effect at CDNLive! in San Jose last year). The other issue is that power management is often seen as the job of the operating system, which depending on the OS, has limited visibility and control of the low-level hardware, thereby creating inefficiencies in power control.

Some help has come from EDA tools using CPF and UPF, which allow the power intent to be specified at the architectural level and then translated down to various IP blocks that are compatible with these power formants. Running a power compiler also helps by reducing leakage current. Although helpful, these techniques need to be coupled with more aggressive forms of power management at the system and architecture level to meet the overall system power requirement.

Ideally, adding a system level power manager IP block will allow access to the lowest level of hardware, and at the same time, be able to communicate with the OS. This IP block will add a level of abstraction for the software, but not sacrifice fast and efficient power domain control. The power manager, when combined with an on-chip-network IP block, will have visibility into every core in the system along with visibility into all the traffic flow. These two combined resources will enable much faster and more reliable wake-up and shut-down of domains since these events will be based on actual traffic (or lack thereof) in each core. Data integrity is also maintained because now systematic shutdown can occur—no data lost!

These kinds of architectural changes are clearly needed for the silicon portion of the phone (at least) to do its part to keep my charger in my laptop bag and not constantly plugged into the wall.

–Frank Ferro is director of marketing at Sonics.